The drain terminals are connected together as a common output. The gate of both the devices are connected together and a common input is given to both the MOSFET device. The source terminal of the N-channel device is connected to the ground. The source terminal of the P-channel device is connected to source voltage +V DD. In CMOS inverter, both the n-channel and p-channel devices are connected in series. a 120-GHz wideband phase-compensated variable gain amplifier (VGA) with a p-type metal-oxide-semiconductor (PMOS) switch using a 40-nm CMOS process. Now let us look at the CMOS logic family. CMOS also has more fan-out and better noise margin. However, the speed of operation is high and power dissipation is less in CMOS. CMOS has greater complexity than PMOS and NMOS. Thus negative voltage(LOW voltage) is enough to turn ON the PMOS devices.ĬMOS(Complementary MOS) logic family uses both N-channel and P-channel MOSFET devices. The operation of PMOS is similar to the NMOS circuits, except that the mode of conduction is different.įor a P-channel MOSFET, a negative voltage is to be given at the gate terminal to create a channel. Similarly, if both the inputs are HIGH, it will turn ON both the MOSFETs, which will make the output to be LOW.Īs discussed above, the digital logic family can be built with P-channel MOSFETs and those circuits are known as PMOS logic circuits. If any of the input, either A or B is given HIGH input, the corresponding MOSFET with HIGH input will turn ON making the output to be LOW.
If Low input is given at both the inputs, it will turn OFF both the MOSFETs Q 2 and Q 3, thereby making the output to be HIGH.
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